1. Technical Field
The present invention relates to multiprocessor systems in general and to a method and apparatus for arbitration between and serialization of plural processors in a multiprocessor system in particular.
2. Description of Prior Art
A multiprocessor system comprises a plurality of processors which are coupled to each other directly or indirectly through one or more other processors. The coupling of processors in such a system comprises the coupling of data and/or control signal buses of one processor and corresponding data and/or control signal buses of one or more other processors in the system. For example, in a multiprocessor system comprising four processors designated first, second, third and fourth, respectively, the processors may be coupled in an arrangement such that the first processor is coupled directly to the second processor and indirectly through the second processor to the third and fourth processors; the second processor is coupled directly to the first and third processors and indirectly through the third processor to the fourth processor; the third processor is coupled directly to the second and fourth processor and indirectly through the second processor to the first processor; and the fourth processor is coupled directly to the third processor and indirectly through the third processor to the second and first processor.
In operation, a central processing unit (CPU) in the system in the course of executing instructions may encounter instructions which require it to request special operations of the other CPU's in the system. For example, some instructions have a requirement that when executed on a CPU the results produced by instructions previously executed on the CPU must be available and visible to other CPUs and channels in the system before the results of the current instruction. Specific results of prior instructions which must be available to other CPU's and channels before the results of a current instruction include storage accesses and translation look aside buffer purge orders. Such an instruction, executed on the requesting CPU, must initiate operations on all other CPU's before the unit of operation on the requesting CPU is completed. A unit of operation is defined as a predetermined amount of work that cannot be interrupted. Furthermore, the operations initiated on each of the other CPU's in the system must be initiated between units of operation on those CPU's. The operations initiated on each of the nonrequesting CPU's, which places all nonrequesting CPU's in a predetermined state, are collectively known as serialization.
In general, the serialization of a processor in a multiprocessor system comprises forcing the processor to complete certain operations and forcing the processor to a state where it will not initiate new operations. For example, operations which are completed during serialization of a processor are specific to each processor, but typically include completing the current unit of operation, completing stores to system memory and local processor caches, and completing any pending updates to local processor translation lookaside buffers.
At times, more than one processor in a multiprocessor system may request serialization of another processor in the system at the same time. When this occurs, the requesting processors must be awarded priority according to a predetermined scheme. The awarding of priority is called arbitration.
The awarding of priority among processors in a multiprocessor system requires special circuits for providing the necessary control signals. Heretofore, the necessary control signals for awarding priority have been generated using a priority logic circuit which is common to all processors in the system. While there are certain advantages in using a common priority logic circuit, it has been found that the use of a common priority logic circuit results in a complex array of control signal lines, unpredictable signal delays and difficulties in maintaining the system in an operable condition because a failure in the common priority circuit affects all CPU's in the system.
Another disadvantage of the prior known arbitration and serialization methods and apparatus was that, heretofore, it was not possible to separate arbitration from serialization so that instructions could protect themselves with the arbitration priority grant mechanism without the overhead of a global serialization. If this had been available, it would have allowed the other CPU's in the system to proceed as normal unless they attempt to perform an operation that also requires arbitration.
In addition to the above-described limitations of prior known arbitration methods and apparatus, prior known arbitration was not possible over multiple instructions. For example, in a certain mode, called Fast Assist Mode (FAM), instructions can be grouped together to function as a single unit of operation. By allowing the arbitration grant to be held over multiple instructions, deadlock conditions which could occur when an instruction needing arbitration or serialization is included in the group of instructions are prevented. Without this facility, either these instructions must be prevented from occurring in FAM with the resulting loss of function, or, when they do occur, the software must cause an exit from FAM to perform the instruction, then a return to FAM once it is completed. Both of these solutions would cause a considerable degradation in performance and/or function compared to the method and apparatus proposed herein.